The present invention relates to a method of manufacturing a wiring substrate.
Generally, metal wiring lines, such as gate electrodes, used in thin film transistors (TFTs) or LSI are formed by etching using photolithography. However, this wiring line forming method requires a plurality of processes, such as forming a resist film and forming a pattern, and increases the manufacturing cost in terms of the manufacturing cost of masks, the disposal cost of a large amount of waste developer, or the like.
In order to cope with these problems, a technique in which a liquid material is coated by using an inkjet method, etc. to form metal wiring lines has recently been developed. Since this technique does not require a high-cost etching process, it is expected to require low cost and to place less burden on the environment. For example, Japanese Unexamined Patent Application Publication No. 2003-315813 discloses a method of manufacturing a wiring film which makes it possible to realize fine lines and increase the adhesion strength of wiring lines to a substrate.
However, when a solution process such as the inkjet method or a vapor deposition method is used, typically, the processing dimension is about 1 to 20 microns. Accordingly, this dimension is insufficient to satisfy the requirement of making wiring lines finer.